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Features
* Dual Core System Integrating an ARM7TDMI ARM Thumb Processor Core and a
mAgic DSP for Audio, Communication and Beam-forming Applications
* High Performance DSP Operating at 100 MHz
- 1 GFLOPS - 1.5 Gops - 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1 Subtract Floating and Fixed Point) Allowing Single Cycle FFT Butterfly - Native Support for Complex Arithmetic and Vectorial SIMD Operations: One Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two Add/sub or Simple Scalar Operations - 32-bit Integer and IEEE 40-bit Extended Precision Floating Point Numeric Format - Large Multi-port Data Register File: 512 Registers Organized in Two 4-input 4output 256-register Banks - Orthogonal VLIW Architecture, Code Compression for Code Size Reduction - Flexible Addressing Capability: 2 Independent Address Generation Units Operating on a 16 Registers Address Register File Supporting Programmable Stride, Circular Pointers and Bit Reversal - 1.7 Mbits of On-chip SRAM: 17 K x 40-bit Data Memory Locations 8 K x 128-bit Program Memory Location, Equivalent to 24K Instructions - DMA Access to the External Program and Data Memory - Two Main Operating Modes: Run and System Mode - Efficient Optimizing Assembler: Allows Easy Exploitation of the Available Hardware Resources Parallelism Utilizes the ARM7TDMI Processor Core with 32 K Byte of Integrated SRAM, Operating at 50 MHz - Fully-programmable External Bus Interface (EBI) Maximum External Address Space of 4 M Bytes Up to 4 Chip Selects Software-programmable 8/16-bit External Data Bus - 8-channel Peripheral Data Controller (PDC) - 8-level Priority, Individually Maskable Vectored Interrupt Controller 4 External, 20 Internal Interrupt Sources, Including a High-priority, Low-latency Interrupt Request - 28 Programmable I/O Lines - 8-channel 11-bit Programmable Clock Prescaler Feeding the Timer, Watchdog, USARTs, SPIs - 3-channel 16-bit Timer/Counter 5 Internal Clock Sources and 3 Configurable Sources (External Source or Cascaded Timer Configuration) 2 Multi-purpose Output Pins plus 1 Output Dedicated to the ADDA Interface plus 3 Outputs Dedicated to the mAgic DSP - 2 USARTs 2 Dedicated Peripheral Data Controller (PDC) Channels per USART 1 USART Supporting Full Modem Interface - 2 Master/Slave SPI Interfaces 2 Dedicated Peripheral Data Controller (PDC) Channels per SPI 8- to 16-bit Programmable Data Length 4 External Slave Chip Selects for each SPI - Programmable Watchdog Timer - ADDA (A/D and D/A Converters) Interface Supporting up to 4 Analog to Digital and 4 Digital to Analog, Stereo 24-bit Converters - IEEE 1149.1 JTAG Boundary Scan on all Active Pins Efficient ARM - DSP Interface Based on 1K x 40-bit Dual Ported Shared Memory, Memory Mapped Register Access, and Interrupt Lines 1.8 V Core Operating Voltage, 3.3 V I/O Operating Voltage On-chip PLL for 100 Mhz Operation from 25 Mhz Reference Clock 352-ball PBGA Package
DIOPSIS 740 Dual Core DSP AT572D740 Summary
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Note: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.
Description
DIOPSIS 740 is a Dual CPU Processor integrating a mAgic DSP and an ARM7TDMITM RISC MCU, plus a total of 245 Kbytes SRAM. The system combines the flexibility of the ARM7TDMI RISC controller with the very high performance of the DSP. mAgic is a high performance VLIW DSP delivering 1 Giga floating-point operations per second (GFLOPS) at a clock rate of 100 MHz. It has 512 data registers, 16 address registers, 10 independent operating units and 2 independent address generation units. For instance, activating all the computing units, it can produce one complete FFT butterfly per cycle. mAgic operates on 32-bit fixed-point and IEEE 754 40-bit extended precision floating-point numeric format. It has also on-chip 17K x 40-bit data memory locations and 8K x 128-bit program memory locations. Efficient usage of the internal program memory is achieved through a code compression mechanism. An optimizing assembler frees the user from the burden of dealing with the parallelism of the processor resources and drastically simplifies the code development. The ARM7TDMITM embedded micro controller core is a member of the Advanced RISC Machines (ARM(R)) family of general purpose 32-bit microprocessors, which offer high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and the related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response. The ARM7TDMITM supports 16-bit Thumb(R) subset of the most commonly used 32-bit instructions. These are expanded at run time with no degradation of system performance. This gives 16-bit code density (saving memory area and cost) coupled with 32-bit processor performance. A rich set of peripheral and a 32 Kbytes internal memory provide a highly flexible and integrated system solution.
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Pin Configuration
Table 1. D740 Ball Assignment (243 I/O)
Name ADDA_BRCK ADDA0_IN ADDA1_IN ADDA2_IN ADDA3_IN ADDA0_OUT ADDA1_OUT ADDA2_OUT ADDA3_OUT ADDA_TOPLL ADDA_WCK ARM_A[0] ARM_A[1] ARM_A[2] ARM_A[3] ARM_A[4] ARM_A[5] ARM_A[6] ARM_A[7] ARM_A[8] ARM_A[9] ARM_A[10] ARM_A[11] ARM_A[12] ARM_A[13] ARM_A[14] ARM_A[15] ARM_A[16] ARM_A[17] ARM_A[18] ARM_D[0] ARM_D[1] ARM_D[2] ARM_D[3] Ball C21 B21 A22 C22 D22 B22 A23 C23 B23 A24 B24 A25 D24 C25 E24 D26 D25 F24 E26 E25 G24 F26 G23 F25 H24 G26 H23 G25 J24 H26 V24 U25 V26 V25 Name ARM_D[6] ARM_D[7] ARM_D[8] ARM_D[9] ARM_D[10] ARM_D[11] ARM_D[12] ARM_D[13] ARM_D[14] ARM_D[15] ARM_NCS0 ARM_NCS1 ARM_NCS2 ARM_NCS3 ARM_NRD ARM_NWEB0 ARM_NWEB1 BIST_RES (dnc) BIST_RUN (dnc) FPU_EXC FPU_HALT FPU_MODE ICE_NTRST ICE_TCK ICE_TDI ICE_TDO ICE_TMS JCFG PIO[0] PIO[1] PIO[2] PIO[3] PIO[4] Notes: 1. PIO[5] Ball W25 Y24 Y26 Y25 AA26 AA24 Y23 AA25 AB26 AB24 H25 J26 K24 J25 K23 K26 L24 H1 H3 AD15 AD13 AE15 K25 M23 L26 N23 M24 M26 AB23 AB25 AC26 AC24 AC25 AD26 Name PIO[8] PIO[9] PIO[10] PIO[11] PIO[12] PIO[13] PIO[14] PIO[15] PIO[16] PIO[17] PIO[18] PIO[19] PIO[20] PIO[21] PIO[22] PIO[23] PIO[24] PIO[25] PIO[26] PIO[27] PLL_CLKIN PLL_CLKOUT PLL_DIV (dnc) PLL_DN (dnc) PLL_EN PLL_LFT PLL_LOCK PLL_TST (dnc) PLL_UP (dnc) RESET SCAN_EN (dnc) SCAN_TEST (dnc) SINGLE SPI0_MISO Ball AD23 AE24 AD22 AC22 AE23 AD21 AF22 AE22 AD20 AF21 AC20 AE21 AD19 AF20 AC19 AE20 AD18 AE19 AF18 AD17 N24 N25 P24 T25 L25 T24 R24 N26 U23 AD14 G2 F1 AE16 C20 Name SPI0_NSS[1] SPI0_NSS[2] SPI0_NSS[3] SPI0_SCK SPI1_MISO SPI1_MOSI SPI1_NSS SPI1_NSS [1] SPI1_NSS [2] SPI1_NSS [3] SPI1_SCK TEST_CLK (dnc) USART0_RXD USART0_SCK USART0_TXD USART1_CTS USART1_DCD USART1_DSR USART1_DTR USART1_RI USART1_RTS USART1_RXD USART1_SCK USART1_TXD XM_A[0] XM_A[1] XM_A[2] XM_A[3] XM_A[4] XM_A[5] XM_A[6] XM_A[7] XM_A[8] XM_A[9] Ball A17 D17 B16 D18 B19 A20 C18 C19 A18 B17 A19 M25 AE17 AF17 AE18 AD12 AE14 AC14 AF14 AF15 AF16 AC15 AD16 AC17 AC12 AE13 AD11 AD10 AE11 AC10 AD9 AE10 AF9 AE9
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Table 1. D740 Ball Assignment (243 I/O) (Continued)
Name ARM_D[4] ARM_D[5] XM_A[12] XM_A[13] XM_A[14] XM_A[15] XM_A[16] XM_A[17] XM_A[18] XM_A[19] XM_A[20] XM_A[21] XM_A[22] XM_A[23] XM_D[1] XM_D[2] XM_D[3] XM_D[4] XM_D[5] XM_D[6] XM_D[7] XM_D[8] XM_D[9] XM_D[10] XM_D[11] XM_D[12] XM_D[13] Ball W24 V23 AC9 AE8 AD7 AF7 AE7 AF6 AC7 AE6 AF5 AD5 AC5 AE5 AB3 AC1 AA3 AB1 AB2 AA1 Y4 AA2 Y1 W4 Y2 W1 V1 Name PIO[6] PIO[7] XM_D[14] XM_D[15] XM_D[16] XM_D[17] XM_D[18] XM_D[19] XM_D[20] XM_D[21] XM_D[22] XM_D[23] XM_D[24] XM_D[25] XM_D[26] XM_D[27] XM_D[28] XM_D[29] XM_D[30] XM_D[31] XM_D[32] XM_D[33] XM_D[34] XM_D[35] XM_D[36] XM_D[37] XM_D[38] Note: Ball AD25 AE26 U3 V2 L1 K3 L2 K4 K1 K2 J1 J2 E3 E4 E2 D1 D3 D2 C1 D5 C11 D12 A11 C12 B11 A12 C13 Name SPI0_MOSI SPI0_NSS XM_D[39] XM_D[40] XM_D[41] XM_D[42] XM_D[43] XM_D[44] XM_D[45] XM_D[46] XM_D[47] XM_D[48] XM_D[49] XM_D[50] XM_D[51] XM_D[52] XM_D[53] XM_D[54] XM_D[55] XM_D[56] XM_D[57] XM_D[58] XM_D[59] XM_D[60] XM_D[61] XM_D[62] XM_D[63] Ball B20 C17 C14 U4 U1 T3 U2 R4 R3 T2 R1 P3 R2 N3 P1 N1 M4 N2 M2 C6 A5 C7 A6 D7 C8 A7 D8 Name XM_A[10] XM_A[11] XM_CLKOUT[0] XM_CLKOUT[1] XM_CLKOUT[2] XM_D[0] XM_D[64] XM_D[65] XM_D[66] XM_D[67] XM_D[68] XM_D[69] XM_D[70] XM_D[71] XM_D[72] XM_D[73] XM_D[74] XM_D[75] XM_D[76] XM_D[77] XM_D[78] XM_D[79] XM_GNT XM_NCS XM_NWE XM_REQ Ball AD8 AF8 J4 H2 G1 AD2 B7 C9 A8 A9 C10 B9 D10 A10 A13 B13 A14 D15 B14 A15 B15 A16 F2 E1 F3 G4
dnc = do not connect pins. These pins are reserved for test use only and are not described in Table 6.
Table 2. D740 Ball Assignment (VDD = 3.3V)
D6 T4 F4 D21 L4 AC16 AC6 AA23 D11 T23 F23 AC21 L23 AC11 D16 AA4
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Table 3. D740 Ball Assignment (VDDI = 1.8V)
B18 E23 B12 B6 T1 W3 AD6 AF11 AF19 AF23 W26
Table 4. D740 Ball Assignment (VDDPLL = 1.8V)
P25 R26
Table 5. D740 Ball Assignment (GND)
A1 H4 AC13 D19 C3 AF26 AE2 V4 D23 A26 B25 W23 D4 AE25 AD3 AC8 AC18 AF25 J23 P23 A2 AE1 D14 C24 B2 B26 AC4 D9 AF1 AD24 N4 AC23
All balls not comprised in Tables 1 to 5 are "not connected".
Pin name conventions
Pin names are built using the following structure: (functional block name) _ (activity level) (line name) (bus index) where: - - - - functional block name = name of the functional block to which the pin belongs activity level = "n" for low active lines; blank for high active lines line name = name of the function of the pin line bus index = number (in [ ]) corresponding to the index when the pin line is an element of a bus
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Pin Description
Table 6. D740 Pin Description
Module ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA ARM ARM ARM ARM ARM ARM ARM ARM ARM mAgic Name ADDA_BRCK ADDA0_IN ADDA1_IN ADDA2_IN ADDA3_IN ADDA0_OUT ADDA1_OUT ADDA2_ OUT ADDA3_ OUT ADDA_TOPLL ADDA_WCK ARM_A[18:0] ARM_D[15:0] ARM_NCS0 ARM_NCS1 ARM_NCS2 ARM_NCS3 ARM_NRD ARM_NWEB0 ARM_NWEB1 FPU_HALT Function ADDA Bit rate clock ADDA 0 input channel ADDA 1 input channel ADDA 2 input channel ADDA 3 input channel ADDA 0 output channel ADDA 1 output channel ADDA 2 output channel ADDA 3 output channel ADDA clock generator Strobe ADDA Word clock ARM external memory address bus ARM external memory data bus ARM external memory Chip select command 0 ARM external memory Chip select command 1 ARM external memory Chip select command 2 ARM external memory Chip select command 3 ARM external Memory Read enable ARM external memory Low Byte Write enable ARM external memory High Byte Write enable ARM Fast IRQ from mAgic "halt" Type in in in in in in in in out-02 out-02 out-03 out-02 bi-02 out-02 out-02 out-02 out-02 bi-02 bi-03 bi-03 out-02 low low low low low low low high data byte d[7:0] data byte d[15:8] To be used for monitoring (internal Pull-Down) Active Level Notes digital serial audio stream bit rate clock (64 x F sampling) 24 bit Left + 24 bit right digital serial stereo audio stream 24 bit Left + 24 bit right digital serial audio stream 24 bit Left + 24 bit right digital serial audio stream 24 bit Left + 24 bit right digital serial audio stream 24 bit Left + 24 bit right digital serial stereo audio stream 24 bit Left + 24 bit right digital serial audio stream 24 bit Left + 24 bit right digital serial audio stream 24 bit Left + 24 bit right digital serial audio stream F Sampling toward an external PLL for ADCs/DACs synchronism generation F Sampling clock toward ADCs/DACs
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Table 6. D740 Pin Description (Continued)
Module mAgic mAgic Name FPU_EXC FPU_MODE Function ARM IRQ15 from mAgic "exception" ARM IRQ25 from mAgic "mode" Type out-02 out-02 Active Level high Notes To be used for monitoring To be used for monitoring 0 = mAgic in system mode 1 = mAgic in run mode low (internal Pull-Up)
JTAG JTAG JTAG JTAG JTAG D740 PIO PLL PLL PLL PLL PLL D740 mAgic
ICE_NTRST ICE_TCK ICE_TDI ICE_TDO ICE_TMS JCFG PIO[27:0] PLL_CLKIN PLL_CLKOUT PLL_EN PLL_LFT PLL_LOCK RESET SINGLE
JTAG Test reset JTAG Test clock JTAG Test data input JTAG Test data output JTAG Test mode ARM JTAG / D740 Boundary Scan selection Parallel Input/Output Reference clock PLL Clock output Pll enable (PLL_CLKIN x4 multiply) PLL lowpass filter input PLL lock condition System reset Single user on mAgic external memory
in in in out-02 in in bi-02 in out-02 in in out-02 in in
(internal Pull-Up)
low
(internal Pull-Up) 0a D740 Boundary Scan 1a ARM JTAG general purpose programmable I/Os or ARM peripheral I/Os 25MHz (max) if PLL_EN =1 100MHz (max) if PLL_EN =0 100MHz (max) if PLL_EN =1 fixed low if PLL_EN = 0
high
1 a system clock = PLL_CLKIN x 4 0 a system clock = PLL_CLKIN
high low high
To be used for monitoring asynchronous (internal Pull-Up) 0 a Not default user of shared XM 1 a Single user of not shared XM or default user of shared XM SPI SLV a data input SPI MST a data output SPI SLV a data output SPI MST a data input SPI SLV a CS Input SPI MST a CS 0 Output SPI SLV a n.a. SPI MST a CS 3, 2, 1 Outputs SPI SLV a clock input SPI MST a clock output SPI SLV a data input SPI MST a data output
SPI SPI SPI SPI SPI SPI
SPI0_MOSI SPI0_MISO SPI0_NSS SPI0_NSS[3:1] SPI0_SCK SPI1_MOSI
SPI 0 Master Out/Slave In data SPI 0 Master In/Slave Out data SPI 0 Input/Output Chip select SPI 0 Output Chip Selects SPI 0 Serial clock SPI 1 Master Out/Slave In data
bi-02 bi-02 bi-02 out-02 bi-03 bi-02
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Table 6. D740 Pin Description (Continued)
Module SPI SPI SPI SPI USART USART USART USART USART USART USART USART USART USART USART USART mAgic mAgic mAgic mAgic mAgic mAgic mAgic Power Power Power Ground Name SPI1_MISO SPI1_NSS SPI1_NSS[3:1] SPI1_SCK USART0_RXD USART0_SCK USART0_TXD USART1_CTS USART1_DCD USART1_DSR USART1_DTR USART1_RI USART1_RTS USART1_RXD USART1_SCK USART1_TXD XM_A[23:0] XM_CLKOUT[ 2:0] XM_D[39:0] XM_D[79:40] XM_GNT XM_NCS XM_NWE VDD VDDI VDDPLL GND Function SPI 1 Master In/Slave Out data SPI 1 Input/Output Chip select SPI 1 Output Chip Selects SPI 1 Serial clock USART 0 Data in USART 0 Serial clock USART 0 Data out USART 1 Clear to send USART 1 Data carriage detect USART 1 Data set ready USART 1 Data terminal ready USART 1 Ring indicator USART 1 Request to send USART 1 Data in USART 1 Serial clock USART 1 Data out mAgic external Memory address bus mAgic external Memory clocks mAgic external Memory data bus mAgic external Memory data bus mAgic shared external memory bus grant mAgic external Memory Chip select mAgic external Memory Write enable IO power supply Core power supply PLL power supply D740 ground reference Type bi-02 bi-02 out-02 bi-03 in bi-03 bi-02 in in in out-02 in out-02 in bi-03 bi-02 out-03 out-03 bi-03 bi-03 out-02 out-03 out-03 Power Power Power Ground high low low 3.3 nominal Supply 1.8 nominal Supply 1.8 nominal Supply common to all Supplies 100MHz (max) One line for up to three mAgic XM chip. Right bank (internal Pull-Down) Left bank (internal Pull-Down) (internal Pull-Down) for synchronous mode only used as output Active Level Notes SPI SLV a data output SPI MST a data input SPI SLV a CS Input SPI MST a CS 0 Output SPI SLV a n.a. SPI MST a CS 3, 2, 1 Outputs SPI SLV a clock input SPI MST a clock output (internal Pull-Down) for synchronous mode only used as output
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Block Diagram
Figure 1. D740 Architecture
32K ARM Memory
Arm7TDMI
ASB / APB Bridge
SPI0
EB I
Amba ASB MAAR Shared Memory Data Bus Mux / Demux
SPI1 USART0 USART1
Program Bus Mux / Demux
TIMER Watchdog
8Kx128 bit Program Memory
mAgic DSP core
Data Memory (6k+6k) x 40 bit Double Bank Double Port
PIO PDC ADDA
Data Buffer 2k + 2k word Double Bank Double Port Data / Program Bus Mux
Clock Gen IRQ Ctrl
Run Mode data paths System Mode data paths ARM exclusive data paths
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Architectural Overview
DIOPSIS 740 (also named D740) is a high performance dual-core processing platform for audio, communication and beam-forming applications, integrating a floating-point DSP (mAgic DSP) and an ARM7TDMITM Reduced Instruction Set Computer (RISC). The D740 is optimally suited for floating point applications with a significant need for complex domain computations like FFT and frequency domain phase-shift algorithms, requiring high dynamic range and maximum numerical precision. The D740 combines the flexibility of the ARM7 RISC controller with the very high performance of the DSP oriented VLIW architecture of mAgic.
System management
The availability of a standard RISC on-chip lowers software development effort for non critical and control segments of the application. ARM7TDMI supports the usage of light RTOS and has efficient interrupt management, leaving mAgic fully available for the numerically intensive part of the application. The synchronization between the two processors can be either based on software polling on semaphores or on interrupts. The ARM is the D740 master processor. The bootstrap sequence of the D740 starts from the bootstrap of the ARM from its external non-volatile memory. The ARM then boots mAgic from a non-volatile memory. After bootstrap the D740 can start its normal operations. The DSP side of many applications can be implemented on the D740 using only the internal memory. In fact the program memory size of 8K by 128-bit coupled with the availability of the code compression, gives an equivalent on-chip program memory size of about 24K instructions (typical). The ARM standard In-Circuit Emulation debug interface is supported via the ICE port.
mAgic DSP Processor
The mAgic DSP is the VLIW numeric processor of the D740. It operates on IEEE 754 40-bit extended precision floating-point and 32-bit integer numeric format. The main components of the DSP subsystem are the core processor, the on-chip memories and the interfaces to and from the ARM subsystem. The operators block, the register file, the address generation unit and the program decoding and sequencing unit compose the core processor. A short description of each block is given in the following paragraphs. mAgic is a VLIW engine, but from an user point of view, it works like a RISC machine by implementing triadic computing operations on data coming from the register file, and data move operations between the local memories and the register file. The operators are pipelined for maximum performance. The pipeline depth depends on the operator used. The operations scheduling and parallelism are automatically defined and managed at compile time by the assembler-optimizer, allowing efficient code execution. In order to give the best support to the RISC-like programming model, mAgic is equipped with a complex 256-entry register file. It can be used as a complex register file (real + imaginary part), or as a dual register file for vectorial operations. When performing single instructions the register file can be used as an ordinary 512 register file. Both the left and right side of the register file are 8-ported, making a total of 16 I/O port available for the data move to and from the operator block and the memory. The total data bandwidth between the register file and the operator block is 70 bytes per clock cycle, avoiding bottlenecks in the data flow between the two units.
Core processor
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Figure 2. mAgic DSP Block Diagram
mAgic - ARM I/F VLIW Program Memory Local Controller and VLIW Decoder
Instruction Decoder Condition Generation Status Register Program Counter
PARM Memory Left 512x40
PARM Memory Right 512x40
Data Register File
Multiple Address Generation Unit Address Register File
Data Memory Left 6Kx40
Data Memory Right 6Kx40
Operator Block DMA Controller Buffer Data Memory Left 2Kx40 Buffer Data Memory Right 2Kx40
External Memory I/F
The operators block, the register file, the address generation unit and the programsequencing unit compose the core processor. The Operators Block contains the hardware that performs arithmetical operations. It works on 32-bit integers and IEEE 754 extended precision 40-bit floating-point data. The Operators Block is composed of four integer/floating point multipliers, an adder, a subtractor and two add-subtract integer/floating point units; moreover, it has two shift/logic units, a Min/Max operator and two seed generators for efficient division and inverse square root computation. The operators block is arranged in order to natively support complex arithmetic (single cycle complex multiply or multiply and add), fast FFT (single cycle butterfly computation) and vectorial computations. The peak performance of mAgic is achieved during single cycle FFT butterfly execution, when mAgic delivers 10 floating-point operations per clock cycle. mAgic is equipped with two independent address generation units. It is able to generate up to two pairs of addresses, one to access the left and the right memory for reading and one to access the left and the right memory for writing. It is also used in the loop control to test if the end of a loop is reached. The Multiple Address Generation Unit (MAGU) supports linear addressing with stride, circular addressing and bit reversed addressing. The address generation unit has 16 registers. The Program Address Generation Unit is devoted to control the correct Program Counter generation according to the program flow. It generates addresses for linear code execution as well as for non-sequential program flow. The Condition Generation Unit combines the flags generated by the operators to produce complex conditions flags used to control the program execution. Predicated instruction execution is supported for different groups of instructions: arithmetical instructions, memory write, immediate load, or all of them. The Program Address Generation Unit also allows to perform conditioned and unconditioned branch instructions, loops, call to subroutines and return from subroutines.
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Internal memories, External memories and DMA
mAgic has four on-chip memory blocks: the Program Memory, the Data Memory, the Data Buffer, and the dual ported memory shared with the ARM processor. An External Memory Interface multiplexes the Data accesses and the Program accesses to and from the External Memory. The Program Memory stores the VLIW program to be executed by mAgic. It is 8K words by 128-bit single port memory. When mAgic is in System Mode the ARM can modify the content of the mAgic Program Memory in two different ways. The ARM can directly write a Program Memory location by accessing the memory address space assigned to the mAgic Program Memory in the ARM memory map. In this access mode the ARM writes four 32-bit words to four consecutive addresses at correct address boundaries, in order to properly complete a single VLIW word write cycle. The ARM can also modify the content of the mAgic Program Memory by initiating a DMA transfer from the External Memory to the mAgic Program Memory. In this access mode a single VLIW word is transferred from the mAgic External Memory to the mAgic Program Memory 64bit per cycle, that is a complete word every two clock cycles. Due to the program compression scheme used, which allows an average program compression between 2 and 3, the code accessing capability of mAgic from its External Memory is greater than an instruction per clock cycle. When mAgic is in Run Mode, the ARM cannot get access to the mAgic Program Memory. When in Run Mode mAgic can initiate a DMA transfer from the External Memory to the mAgic Program Memory to load a new code segment. The mAgic internal Data Memory is made of three memory pages, 2K words by 40-bit for the left data memory and 2K words by 40-bit for the right data memory, giving a total of 6K words for the left and for the right memory banks (a total of 12K words ). Each Data Memory bank is a dual port memory that allows four simultaneous accesses, two read and two write. The core can access vectorial and single data stored in the Data Memory. Accessing complex data is equivalent to accessing vectorial data. During simultaneous read and write memory accesses, the MAGU generates two independent read and write addresses common to both the left and the right memory banks. The total available bandwidth between the Register File and the Data Memory is 20 bytes per clock cycle, allowing full speed implementation of numerically intensive algorithms (e.g. complex FFT and FIR). The Buffer Memory is 2K words by 40-bit for both the left and the right memory. The Buffer Memory is a dual port memory. A port is connected to the core processor. The MAGU generates the Buffer Memory addresses for transferring data to and from the core. The second port of the Buffer Memory is connected to the External Memory Interface. The Buffer Memory does not support dual read and write accesses neither from the core nor from the External Memory Interface. The available bandwidth between the core processor and the Buffer Memory is equal to the available bandwidth between the External Memory Interface and the Buffer Memory: 10 bytes per clock cycle. The maximum External Memory size of mAgic is 16 Mword Left and Right (equivalent to 32 Mword or 160 Mbytes; 24-bit address bus). A DMA controller manages the data transfer between the External Memory and the Buffer Memory. The DMA controller can generate accesses with stride for the External Memory. The DMA transfers to and from the Buffer Memory can be executed in parallel with the full speed core instructions execution with zero-overhead and without the intervention of the core processor, except for initiating it. The last memory block in the address space of the mAgic DSP is the memory shared (PARM) between mAgic and the ARM processor. It is a dual port memory 512 words by 40- bit for both the left and the right bank (total 1K by 40-bit). This memory can be used to efficiently transfer data between the two processors. The available bandwidth between the core processor and the shared memory is 10 bytes per clock cycle. On the
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AT572D740
ARM side the available bandwidth is limited by the bus size of the ARM processor (32 bits) giving a bandwidth of 4 bytes per ARM clock cycle. ARM interface (mAAr) The D740 master is the ARM7 RISC processor. mAgic behaves as a standard AMBA ASB slave device, allowing access to different resources depending on the operating mode (Run or System). In System Mode, mAgic halts its execution and the ARM takes control of it. When mAgic is in System mode the ARM can access many mAgic internal devices. The ability of the ARM to access internal mAgic resources in System Mode can be used for initialization and debugging purposes. By accessing the Command Register, the ARM can change the operating status of the DSP (Run/System Mode), initiate DMA transactions, force single or multiple step execution, or simply read the DSP operating status. In Run Mode, mAgic works under direct control of its own VLIW program and the ARM has access only to the 1K x 40-bit dual ported shared memory (PARM) and to the mAgic Command Register. In order to allow a tight coupling between the operations of mAgic and the ARM at run time, they can exchange synchronization signals, based on interrupts.
ARM System: ARM7TDMI The ARM7TDMI is a 32-bit RISC microprocessor; it is a member of the Advanced RISC Machines (ARM) family of general-purpose 32-bit microprocessors, offering high perforProcessor and mance and very low power consumption. Peripherals
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and a real-time interrupt response. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. The typical operating scheme of the ARM7TDMI is the sequence fetch-decode-execute. The ARM7TDMI processor employs the architectural strategy known as THUMB. THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. The 16-bit instructions are expanded at run time with no degradation of the system performance. This provides far better performance than a 16-bit architecture, with better code density than a 32-bit architecture. The ARM7TDMI processor is built around a bank of 37 32-bit registers and six status registers. The ARM7TDMI supports seven operation modes: 1. User (usr): The normal ARM program execution state 2. FIQ (fiq): Fast Interrupt reQuest; it is connected to the mAgic Halt signal 3. IRQ (irq): Used for general-purpose interrupt handling 4. Supervisor (svc): Protected mode for the operating system 5. Abort mode (abt): Entered after data or instruction prefetch abort 6. System (sys): A privileged user mode for the operating system 7. Undefined (und):Entered when an undefined instruction is executed Mode changes can be made under software control or can be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes - known as privileged modes - are entered in order to service interrupts or exceptions, or to access protected resources. Each operating mode has dedicated banked registers for fast exception handling. The FIQ mode has five addi-
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tional banked working registers, r8_fiq to r12_fiq, to enhance interrupt processing speed. The ARM7TDMI processor operates in little-endian mode. To speed-up critical routine execution or critical data segment access, the ARM7 is equipped with 32 Kbyte of zero wait states on-chip memory. The ARM system has two buses. The main bus is the ASB (ARM System Bus). The APB (ARM Peripheral Bus) is designed for accesses to on-chip peripherals. The AMBA Bridge provides an interface between the ASB and the APB. The D740 is equipped with a set of peripherals controlled by the ARM. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories in the DMA without the intervention of the processor. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for data transfer. Each peripheral has a 16K-byte address space allocated in the upper 3M bytes of the 4Gbyte address space. The peripheral register set is composed of control, mode, data, status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. A short description of the available peripherals is given in the following. * * * EBI (External Bus Interface): the EBI generates the signals that control the access to the External Memory or peripheral devices. ADDA (Analog to Digital and Digital to Analog interface): the ADDA provides 4 channel serial interface toward stereo audio 24-bit ADC and DAC. PDC (Peripheral Data Controller): The PDC provides 8 communication channels dedicated to the two USARTs and to the two SPIs. One PDC channel is connected to the receiving channel and the one to the transmitting channel of each peripheral. USART (Universal Synchronous / Asynchronous Receiver / Transmitter): two, fullduplex, universal synchronous/asynchronous receiver/transmitters provide a simple standard communication way managed by the Peripheral Data Controller. SPI (Serial Peripheral Interface): two four-wire serial interfaces provide a simple industry-standard communication way managed by the Peripheral Data Controller. AIC (Advanced Interrupt Controller): the AIC is an 8-level priority, individuallymaskable, vectored interrupt controller. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. PIO (Parallel I/O Controller): The PIO features 32 programmable I/O lines, 28 PIO lines are available on D740 pads, while the remaining 4 are only internal. TC (Timer Counter): the TC contains three identical 16-bit timer/counter channels. WD (Watchdog Timer): the WD can be used to guard against system lock-up if the software becomes trapped in a deadlock. If an overflow occurs, the watchdog timer generates processor interrupts via the Advanced Interrupt Controller (AIC) and an external low pulse through the PIO. CLKGEN (Clock Generator): The clock generator provides divided clocks for several peripherals: the Timer Counter, the Watchdog, the USARTs and the SPIs.
*
* *
* * *
*
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AT572D740
Figure 3. Armsystem Architecture
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Development Tools
D740 is supported with a complete set of software and hardware development tools. MADE The D740 is supported by a set of development tools integrated into a visual development environment called MADE (Multicore Application Development Environment). MADE provides the user with an integrated environment for producing applications for both the D740 cores, the ARM7TDMI and the mAgic DSP, by means of a common project management and support for the MARMOS Minimal Bios. Code generation tools for the ARM include the GNU Code Development Chain for ARM7 (C-C++ compiler, assembler, linker and utilities) and the ARM SDT Code Development Chain (C-C++ compiler, assembler, linker and utilities). Code generation tools for mAgic include C compiler (GNU gcc based, ANSI compliant), VLIW assembler-optimizer, code compressor, linker and utilities. MADE supports the MARMOS Minimal Bios, a set of helper functions for the ARMmAgic intercommunication and the D740 peripherals management. MARMOS gives the user the basic APIs for building an integrated ARM-mAgic application. MADE provides the user with a simulation engine and an emulation kernel: the CycleAccurate simulator and the D740 emulator board support. JTAG-ICE The ARM Standard In-Circuit-Emulation debug interface is supported via the JTAG-ICE port of the D740. When the ARM ICE configuration is selected, the usual debug capabilities for the ARM System are supported, while the support for the mAgic core is limited to memory and status registers inspection. The 5 jtag pins are shared between ARM7TDMI ICE functionality and the DIOPSIS 740 chip Boundary Scan Logic. The "JCFG" pin acts as ARM jtag / D740 BSL selector. When "JCFG" pin is high the ARM ICE is selected, while DIOPSIS 740 BSL is selected when "JCFG" is low. JTST
JTST is a low cost general-purpose module that provides the appropriate resources in order to test DIOPSIS 740. JTST provides the following resources to DIOPSIS 740:
- - - - - - - - - - -
mAgic SSRAM, ARM FLASH and SRAM 4 Stereo Audio 20 bit CODECs 1 USB 2.0 Full (12 Mbps) 2 RS232/LVTTL a/synchronous serial I/O lines 2 SPI serial I/O lines Reset Logic (Power ON, Push Button, WDG) IO connectors (USART, SPI, USB, PIO, AUDIO) PLL-Clock Logic (25 MHz oscillator + CLK connector) DIP SWITCH & Status 7-segment Display Voltage Regulators 5V/3.3V & 5V/1.8V M-ICE JTAG
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AT572D740
Mechanical Drawing
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Table 7. D740 Dimensions (mm)
Symbol A1 b aaa bbb ccc ddd eee A Dim "B" e REF D/E D1/E1 f REF J/L REF 34.8 2.12 0.44 Min 0.50 0.60 Nom 0.60 0.75 0.30 0.25 0.35 0.30 0.15 2.33 0.52 1.27 35.0 30.0 11.0 1.62 35.2 30.7 2.56 0.60 Max 0.70 0.90
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AT572D740
Power Dissipation
The D740 has three kinds of power supply pins: * * * VDDCORE pins, which power the chip core (1.8V) VDDIO pins, which power the I/O lines (3.3V) VDDPLL pins, which power the oscillator and PLL cells (1.8V)
The total power dissipation is the sum of two basic contributions: PD = PIO + PCORE PIO represents the contribute due to the IO pads current and the output load current. PCORE represents the contribute due to the internal activity current. The following table defines the current consumption on different conditions: Table 8. Power Dissipation
Parameters typical conditions Idd IO (3.3V) mA Idd peak Idd high Idd no ext Idd sys mode Idd rst 330 120 25 25 10 Idd CORE (1.8V) mA 460 400 390 100 160 worst conditions Idd IO (3.3V) mA 425 155 35 35 15 Idd CORE (1.8V) mA 600 520 500 135 205
* * * * * * *
Idd peak = mAgic FFT; both mAgic and ARM ext mem written 100% with continuous toggling data Idd high = mAgic FFT; both mAgic and ARM ext mem read and written alternatively 100% with 50% toggling data Idd no ext = mAgic FFT; ARM FLASH access 100%; no mAgic ext mem access Idd sys mode = mAgic in system mode; ARM FLASH accesses 100%; Idd rst = D740 under reset typical condition = typical process; Tj = 25; Vdd = nom worst condition = worst process; Tj = 100; Vdd = nom + 10%
To estimate power consumption for a specific application use the following equation where % is the amount of time your program spends in that state and each "Idd" contribute corresponds to "IO" or "CORE" columns: PCORE = ((%peak x Idd peak) + (%high x Idd high) + (%no ext x Idd no ext) + (%sys mode x Idd sys mode) + (%rst x Idd rst)) x 1.8 PIO = ((%peak x Idd peak) + (%high x Idd mode) + (%rst x Idd rst)) x 3.3
Note:
high)
+ (%no ext x Idd no ext) + (%sys mode x Idd
sys
Idd peak represents worst-case processor operation (for Idd IO particularly) and it is not considerable for also for hard applications where all data bits do not toggle every cycle.
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Reliability Data
The following table summarizes some basic data that can be used in reliability calculations. Table 9. Silicon Block Size
Parameters Logic Gates Memories Register File total Device Die Size (pad excluded) Data 585 12 0.3 Unit Kgates M transistors M transistors Data 10.5 18 5.1 45 Unit mm2 mm2 mm2 mm2
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AT572D740
Ordering Guide
Table 10. Ordering Information
Part Number AT572D740 Temperature Range 0C - 70C Working Frequency 100 MHz Operating Supplies 3.3V (I/O) & 1.8V (core) Package 352PBGA
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